Micrologic Design Automation announced the BETA release of VisuaLVS™             Layout vs. Schematic Automatic Correction System

Haifa, Israel: January 24, 2008 - Micrologic Design Automation, Inc., a leading provider of EDA solutions for nanometer IC design, today announced the beta release of VisuaLVS™, Interactive Layout vs. Schematic Correction system for IC’s layout. 

VisuaLVS™ is an EDA tool that automatically corrects connectivity mismatches in an integrated circuit layout block. The tool reads the IC layout block’s industry standard LVS check results, its netlist and constraints (if exists) and automatically corrects connectivity mismatches, maintaining the process design rule correctness. In addition, VisuaLVS™ supports timing and DFM along with process topological rules providing a real-time LVS correction environment.

The tool is offered under NanoToolBox™(NTB) tools suite which enabling significant productivity enhancement platform within chip design cycle and is a plug-in into Cadence(R) Virtuoso(R) custom design platform.

"VisuaLVS™ is an entire new concept in IC’s LVS verification methodology. The tool provides an advanced approach in order to easily analyze each LVS violation and thus can offer an immediate correction. Semiconductor corporations have the capability to meet or shorten time-to-market objectives and improve their design quality and performance. Therefore, handling multimillion-gate projects with significant higher productivity!” stated Danny Rittman, President & CTO of Micrologic. "With our industry-leading customer service and commitment to provide Micrologic products and solutions, we are able to support IC designer’s requirements, as well as design flow enhancements to increase the productivity of our customers."

VisuaLVS™ supports digital, analog and mixed-signal IC’s design style and available in a wide variety of packages according to customer’s request.

About Micrologic, Inc.

Micrologic Design Automation, Inc. develops semiconductor design software for electronic design automation, (EDA) intellectual property (IP) and design for manufacturing (DFM) solutions enabling integrated circuit corporations to meet or shorten time-to-market objectives, improve nanometer designs quality, reliability and performance and handling multimillion-gate designs. The company’s products enable semiconductor companies to increase productivity and achieve predictable success from systems to silicon.

Micrologic’s web site: www.micrologic-da.com

VisuaLVS™ is trademark of Micrologic Corporation. All other trademarks and registered trademarks in this document are the properties of their respective owners.

* Virtuoso is a trademark of Cadence Corporation.