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NanoToolBox™ Suite
The NanoToolBox Suite solves the IC verification bottleneck problem.
Each of the three products in the NanoToolBox Suite integrate with Cadence Virtuoso® and other design EDA systems to bring your custom IC design environment a giant step forward towards correct-by-construction perfection. NanoToolBox gives you the competitive edge you need to bring you nanometer chip designs to signoff faster with fewer design cycles, greater reliability and higher performance
The IC verification bottleneck problem is caused by non-interactive integration among the final three IC design steps: physical layout, verification and correction.
The verification bottleneck problem is three-fold:
1. Physical layouts produced by Cadence Virtuoso and other interactive custom IC design environments are not perfectly correct by construction. The layout database must clear a separate verification step before the IC can be fabricated.
2. Verification takes a long time to perform particularly with large data and verification rules becoming more complex as dimensions shrink from 45 nanometers to 32 nm and smaller.
4. Correcting layout errors is very labor intensive and time consuming. The correction-verification cycle must be repeated over and over again until the physical design is clean and passes signoff.
Verification is a serious growing bottleneck problem in the semiconductor industry.
The NanoToolBox Suite has three complementary products to solve your verification bottleneck problem. Learning how to use the NanoToolBox is a snap because the tools are built right into Virtuoso. Add one, two or all three products to your Cadence Virtuoso design environment and in no time at all you’ll be reaching signoff faster with fewer design cycles, greater reliability and higher performance!
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