Micrologic Design Automation

VisuaLVS™

Interactive Layout vs. Schematic Correction system

VisuaLVS™ is a nanometer range EDA tool that corrects connectivity mismatches in an integrated circuit layout block. The tool reads the IC layout block’s industry standard LVS check results and its netlist and automatically corrects connectivity mismatches, maintaining the process design rule correctness. In addition, VisuaLVS™ provides a real-time LVS correction environment within Cadence’s layout editor. (Virtuoso LE, XL, GXL)

VisuaLVS™ is aimed for rapid, accurate, and efficient automatic correction of connectivity mismatches in a mask layout database. VisuaLVS™ reads the layout block’s netlist and LVS check results, comparing the information with the block’s physical layout. In the instance of connectivity mismatches, the tool suggests correct alternative connections. Upon user’s approval VisuaLVS™ disconnects existing nodes and replaces them with the new connections, maintaining the process design rule correctness.

Benefits

Significantly reduces LVS verification time - During the construction of a mask layout block, VisuaLVS™ reads the built-in layout editor’s database, compares it to its netlist and provides interactive suggestions and alternative corrections according to current connectivity status. Each suggestion and alternative correction is accompanied with full detailed report about the found mismatch.

VisuaLVS™ - Innovative EDA software which is based on recent real-time technology. This program is a plug-in into Cadence’s Virtuoso platform, enabling the interactive/independent LVS (Layout versus Schematic) correction environment. The program reads a circuit netlist and the result of LVS check (From the Industry’s standard LVS checkers) and automatically corrects its layout’s LVS mismatches.

VisuaLVS™ provides you with a clear and immediate graphical representation of your design’s connectivity analysis, before and after correction.

VisuaLVS™ is an interactive nanometer productivity tool that is part of the NanoToolBox™ (NTB) tools suite and can easily interchange information with all of our other interactive NanoToolBox™ tools.

VisuaLVS™ interfaces with Cadence’s Virtuoso via SKILL and OpenAccess. In addition, the system offers key function access via API calls for customization and personalization purposes.

VisuaLVS™ fully supports OpenAccess for future interoperability and enhancements.

In order to ensure versatility, our tool fully supports OpenAccess enabling interaction with industry’s standard scripting languages, providing full customization possibilities.

Features

VisuaLVS™- An entire new concept in integrated circuit LVS verification methodology. Our software provides an advanced approach in order to easily analyze each LVS violation and provide an immediate correction.

VisuaLVS™ works in flat and/or Hierarchical mode. In flat mode VisuaLVS™ detects mismatches only at the current edited level. In hierarchical mode the tool checks for connectivity correctness through all block levels. The main advantage of this concept is the creation of a Connectivity-Aware IC layout design environment that eliminates ahead of time connectivity issues that may consume significant LVS verification time later in the design flow. The system provides a powerful tool that eliminates LVS issues during the integrated circuit physical design phase.

VisuaLVS™- Information Window - Quick description fields enable users to get all desired details about any LVS violation and its suggested correction. The Information Window enables users to quickly assess the nature of the LVS issue and provide vital information about current and suggested net correction.

VisuaLVS™ - Assist Mode allowing the user to work in a non-invasive manner detecting LVS problems during the construction of a mask layout block and recommending alternative connectivity options in order to correct the mismatch.

VisuaLVS™- Auto Correct Mode – This mode provides automatic correction of LVS violations in a layout block. The tool reads the LVS check results and the block’s netlist and automatically corrects all layout LVS violations, maintaining the process design rule accuracy.

VisuaLVS™- Stage Correction - User may correct LVS violations serially. The system graphically presents the violation and offers a solution. The user may accept or reject the suggested solution according to desire.

VisuaLVS™- Full nanometer support, including deep nanometer ranges.

VisuaLVS™ - Advanced viewing system provides an accurate graphical representation of LVS violations within the Virtuoso design environment, including a secure recovery mechanism to keep the block’s LVS information in the event of system crash or data corruption.

VisuaLVS™ - Universal & Fully Customizable. Users can customize and personalize their options

VisuaLVS™ - Supports digital. Analog and mixed signal designs.

Specifications

ü Automatic correction of connectivity mismatches in a mask layout database.

ü The tool reads industry standard LVS check results files and NETLIST.

ü The tool reads industry standard technology and run sets files. (Process design rules)

ü Advanced viewing system provides real-time graphical representation of connectivity mismatches.

ü Assist mode to guide users about potential connectivity mismatches during the construction of an IC’s mask layout database and suggested solution.

ü Auto-Correct mode to automatically correct connectivity mismatches during the construction or independently of an IC’s layout database, maintaining process design rules!

ü Flat and fully Hierarchical analysis.

ü Suggests alternative connections. The user has the choice of selecting the best connection in order to eliminate connectivity mismatch.

ü Rapid description fields provide comprehensive information about found connectivity problems and suggest methods for correction.

ü Stage Correction allows selective connectivity problem correction.

ü Advanced graphical setup for easy identification of potential connectivity mismatches.

ü Full nanometer support, including deep nanometer ranges.

ü Universal & Fully Customizable. Users can customize and personalize his/her analysis/correction options.

ü OpenAccess support further contributes to open interoperability and ensures ease of tool integration for customers.

ü Exclusively developed for Cadence’s Virtuoso platform. (Virtuoso LE/XL/GXL)

ü Exporting & importing of design parameters from related Cadence tools and environments in order to provide all necessary analysis and auto-correction information.

ü The tool is an integral part of our NanoToolBox™ suite and shares the design information with all our other suite tools.

ü Supports all design types, including digital, analog and mixed signal designs.

Design Inputs

Ø All Cadences’ Virtuoso supported formats (Layout database)

Ø Industry standard LVS check log file (Results of LVS run)

Ø Industry standard NETLIST

Ø Industry standard run sets/rule decks (Process Design Rules)

Design Outputs

Ø Graphical representation of potential & existing connectivity mismatches

Ø Connectivity mismatches analysis reports

Platforms/OS

Ø Sun/Solaris